1. Field of the Invention
The present invention relates to a semiconductor memory device, and, particularly, to the semiconductor memory device using a ferroelectric capacitor.
2. Description of the Related Art
A ferroelectric memory device (FeRAM) is a semiconductor memory device that may store data in a non-volatilile manner based on two different magnitudes of ferroelectric polarization using hysteresis properties of the ferroelectric capacitor.
Generally, memory cells in the conventional ferroelectric memory employ architecture similar to DRAM. That is, a paraelectric capacitor is replaced with a ferroelectric capacitor, and a ferroelectric capacitor and a select transistor are connected in series to form a memory cell (refer to Japanese Patent Laid-Open No. 2001-250376). Such the memory cells are arranged in a grid to form a memory cell array. On reading data or the like, a word line (a select line) of the memory cell to be read is activated, and a select transistor is made conductive, thereby connecting a memory cell to a bit line.
In addition, a so-called TC parallel unit series-connected type ferroelectric memory is also known. This memory is configured by connecting a cell transistor and a ferroelectric capacitor in parallel to form one memory cell, and such memory cells are connected in series to form a memory cell block (refer to JP 2005-4811A). Both in the DRAM-like structure and in the TC parallel unit series-connected type, two methods can be adopted, respectively. One of the methods is called 2-2 transistor-cell method. This method reads complementary data from two memory cells in the dielectric memory (2T2C method). Another one is called 1-1 transistor-cell method (1T1C method). This method uses a single memory cell, and a comparison and amplification of the signal is made with a reference voltage supplied from a dummy capacitor.
A case where a DRAM-like structure is employed is explained herein as an example.
When the 2T2C method is adopted in the DRAM-like structure, a word line connected to a memory cell to be read, and a word lone connected to a complementary memory cell holding a complementary data are selected. Then, the memory cell and the bit line are connected, and the complementary memory cell and the complementary bit line are connected. Thereafter, the plate line voltage is applied to a plate line, thereby applying a voltage to both ends of a ferroelectric capacitor included in the memory cell and the complementary memory cell. The electric charge from the ferroelectric capacitor of the memory cell is read to a bit line, whereas the electric charge from the ferroelectric capacitor of the complementary memory cell is read to a complementary bit line. Then, the potential of these bit line pair is compared and amplified by a sense amplifier.
On the other hand, in the 1T1C method, a word line connected to a memory cell to be read is selected, and the memory cell and the bit line are connected. Then, the plate voltage is applied to a plate line connected to a memory cell, and the voltage is applied to the both ends of a ferroelectric capacitor included in a memory cell. A reference voltage is thereby supplied to a complementary bit line included in bit line pairs from a dummy capacitor. Electric charge from a ferroelectric capacitor is read to a bit line. The potential of the bit line pairs is compared and amplified by a sense amplifier.
Dummy capacitors are usually used in common for plural memory mats activated at the same time in one memory chip. However, a amount of a signal provided from a memory cell may vary among different memory mats. In this case, it is sometimes difficult, with only one dummy capacitor in a memory cell array, to set an adequate reference voltage while maintaining a preferable margin.